Evaluation Designs
At this location the Josef Ressel Center INES aims to collect open-source projects that can be useful for evaluations or to test design/tool flows. This site is subject to permanent further development.
Logic Simulation
The following designs may be useful if there a need for real-world projects in context to digital logic simulation. All designs inlude a testbench as well. All testbenches that are part the projects shown below stop automatically, there is no need to define a "simulation end time".
| Design/Testbench Language | Name of Top-Level Testbench | Description and Download Link | |
| AC97 Controller IP Core | Verilog | test | An audio codec that is compliant to the Intel AC97 standard. The project can be found here (original design) or here (local mirror). |
| Ethernet MAC 10/100 Mbps | Verilog | tb_ethernet | A 10/100 Mbps Ethernet MAC (Media Access Controller) with a comprehensive testbench setup. The project can be found here (original design) or here (local mirror). |
| Full Adder | both VHDL and Verilog implementations exist | tb_fulladder_sim_cfg (VHDL version), tb_fulladder (Verilog version) | A very simple full adder, just for basic tests. The project can be found here. |
| LEON3 | mixed VHDL/Verilog design including PSL code | testbench | The original LEON3 CPU core can be found here while the demo design that makes use of that core can be dowloaded from here. |
| MC8051 CPU Core | VHDL behavioral model, Verilog post-synthesis netlist (no timing) and SDF-annotated netlist exist | tb_mc8051 | Derivate of the well known 8-bit microcontroller mc8051 from Intel. Some peripherals (clock prescaler, reset logic …) have been added to the original project. Three versions of this design exist: (i) VHDL behavioral model, (ii) post-synthesis Verilog netlist (no timing) and (iii) SDF-annotated post-synthesis Verilog netlist. Versions (ii) and (iii) have been synthesized to a Xilinx Artix-7 FPGA by using Xilinx Vivado 2018.2. The original MC8051 CPU core can be found here while the demo design that makes use of that core can be dowloaded from here. |
| OCIDEC (OpenCores IDE Controller) | Verilog | test | A Parallel ATA/ATAPI-5 (also known as IDE) compliant host implementation. The project can be found here (original design) or here (local mirror). |
| PCI Bridge | Verilog | SYSTEM | A fully PCI 2.2 compliant 32-bit PCI interface. The project can be found here (original design) or here (local mirror). |
| PicoRV32 CPU Core | Verilog | system_tb | A 32-bit CPU core that implements the RISC-V RV32IMC instruction set. The project can be found here (original design) or here (local mirror). |
| SHA256 Hash Core | VHDL | testbench | An implementation of SHA (Secure Hash Algorithm) 256 which is a well-known cryptographic hash function. The project can be found here (original design) or here (local mirror). |
| Viterbi Decoder | VHDL | tb_dec_viterbi | A Viterbi decoder with self-checking testbench. The project can be found here (original design) or here (local mirror). |
| Wishbone ConMax IP Core | Verilog | test | An implementation of an interconnect matrix for the Wishbone SoC bus. The project can be found here (original design) or here (local mirror). |
Logic Synthesis
To be announced ...