Prototype Implementations of the COORDES Concept
In the COORDES concept several units are to be added to an embedded node, typically and most effectively on chip level, to keep the task of debugging in the background and to minimize or cancel the probe effect. This is also true for the clock synchronization mechanism. A node constructed according to the proposed concept thus contains a clock unit, a test unit, a fault injection unit, a replay unit, a trace unit, a debug unit and an offload engine, which controls the aforementioned units. The units are connected to the offload engine via a separate bus ("Debug Bus"). Furthermore, a network interface which is capable of filtering the incoming messages is connected to the offload engine as well as to the application CPU, see figure below.
The network interface receives and transmits packets via the network. The built-in filter detects incoming messages that contain debugging commands or clock synchronization information and directs those messages to the offload engine. Other messages are forwarded to the application CPU which is unaware of the filtering mechanism. Concerning transmissions the network interface has the ability to insert packets containing information related to debug and test from the offload engine into the transmit buffers during idle times.
The presented solution has been successfully integrated into a multi-node FPGA-based proof of concept based on single core 32-bit CPUs and is now integrated into a 90 nm CMOS ASIC to proof the fitness of the approach for industrial use. IEEE 1588 is used for clock synchronization in the 10 ns range over an Ethernet local area network. Furthermore, the new functions for coordinated debug have been fully integrated into an Eclipse IDE to allow state-of-the art source-level debug of several embedded systems in parallel.