• Contact
• Legal Notice

• Staff
• Services
• Research & Development
• Publications
• Partners
• Career

Research Group
Embedded Systems

The proposed platform for the gateway nodes is based on common off-the-shelf development boards using FPGA technology. This provides the most flexibility together with the minimum cost.

The compulsory supported bus technologies are CAN, FlexRay and Ethernet. LIN and TTP are supported optionally. For Ethernet the support of a star topology with one central Ethernet switch is sufficient. For FlexRay bus and star topologies are required. For CAN, LIN and TTP only bus topologies have to be supported.

The following figure shows the Xilinx Virtex-4 off-the-shelf base board and a daughter board which was developed at our department.

The FPGA contained on the base board implements powerful 32 bit PPC and Xilinx Micoblaze CPUs which are capable to run an embedded operating system (Embedded Linux, uC-OS, uC-Linux, or the like) in order to offer a stable and flexible platform for the integration of the various communication protocols.

The physical layer interfaces are situated on the daughter board. The daughter board has CAN and FlexRay physical layer interfaces via several Sub-D jacks. To support testing and debugging of communication traffic it is essential to make the physical layer output data visible not only to the connected link layer controller but also to the debugging and testing circuitry located either in the base board FPGA or in a second FPGA which is implemented on the daughter board. The daughter board allows to access the physical layer receive and transmit data, so that faults can be injected anywhere in a data packet. The daughter board also includes an expansion header to connect other network circuitry (e.g., LIN transceivers) to the board (due to lack of space it was not possible to add another network controller or transceiver directly on the PCB).

To allow reproducible and sound measurements and to support distributed testing and debugging, a means to precisely synchronize the local clocks of the gateway nodes has to be implemented. For Ethernet networks this can be an IEEE 1588 compatible mechanism.

In contrast to most available gateways the platform described above can be configured and expanded to a high degree concerning both hardware and software by using a programmable system-on-chip architecture. The proposed solution is not limited to gateway applications but provides a generic platform for the development of network infrastructure in the automotive area.