Competence Team for Design- and Verification-Patterns for Embedded Systems

These days, the majority of embedded systems engineers still designing, programming, and verifying embedded software on single-core embedded microcontrollers. As new technology trends emerge, more and more embedded chip vendors altering towards multi-core technology, in terms of trying to provide sustainable performance enhancement by simultaneously lowering chip power consumption.

Therefore, an embedded software designer, who is responsible for programming such new multi-core chips, are now facing new design challenges due to the inherent parallelism of two or more cores running simultaneously.

The aim of the project is to develop strategies for new design- and verification-patterns tailored towards asymmetric multiprocessing paradigm. Furthermore, the project objective is to transfer the findings and lessons learned throughout the competence team into the department's undergraduate and graduate courses.

The competence team design- and verification-patterns for embedded systems is part of the Research Group Embedded Systems at the University of Applied Sciences Technikum Wien.

This project is funded by the City of Vienna, department MA27, under grant number MA 27-Projekt 10-09.

Project Duration: 01.09.2010 - 31.8.2013